Senior Digital ASIC Verification Engineer (m­­/­­f­­/­­d)

A degree in Electronic Engineering, Microelectronics , or equivalent field of studies At least 5 years of experience in mixed-signal and digital verification of IC designs or equivalent verification field Good experience with EDA tools for mixed-signal and digital verification (Cadence AMS-Designer/XCelium, Synopsys VCS/XA) and test bench concepts and methodologies (UVM) Profound knowledge of standard SW programming languages, HDL languages (focus on System Verilog), plus the ability to write synthesize-able, behavioral code and real-number modelling Ability to implement and test scripts (Python, Perl, Shell) An independent and autonomous working style , with the ability to collaborate effectively within an international team Fluency in English